1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of controlling the operation of a semiconductor device.
2. Description of the Related Art
Non-volatile memories are memory devices that store information as data and can hold the data in storage even after the power supply is cut off. Flash memories are rewritable non-volatile memories and typically include a floating gate through which electrons are injected or drawn out so as to perform writing or erasing.
Y. Sasago, et al, disclose an AG-AND-type flash memory that has a floating gate but does not have a diffusion layer in “90-nm-node multi-level AG-AND type flash memory with cell size of true 2F 2/bit and programming throughput of 10 MB/s (December 2003, Technical Digest, pp. 823-826)”. FIG. 1 is a plan view of the memory array of an AG-AND flash memory for the 90-nm-node as disclosed in Y. Sasago, et al. FIG. 2A is a cross-sectional view of the memory array of FIG. 1 illustrating the voltage conditions at the time of programming. FIG. 2B is a cross-sectional view of the memory array of FIG. 1 illustrating the voltage conditions at the time of reading. FIG. 3 illustrates the AG-AND array structure as disclosed in Y. Sasago, et al.
Assist gates AG0 through AG3 are provided on a silicon substrate and an inversion layer (a channel) is formed on the substrate therebelow. Therefore, a diffusion layer does not exist in this structure. Word lines WL extend in a direction perpendicular to the assist gates AG. During a programming operation, voltages of 0V, 5V, 1V, and 8V are supplied to the assist gates AG0, AG1, AG2, and AG3, respectively, and a voltage of 18V is supplied to the word lines WL of a selected cell as shown in FIG. 2A.
A channel that serves as a source is formed under the assist gate AG1 to which the voltage of 5V is applied and a channel that serves as a drain is formed under the assist gate AG3 to which the voltage of 8V is applied. The channel under the assist gate AG2 to which the voltage of 1V is applied becomes weak, so that the electric field on the boundary with the floating gate FG is intensified and the current is restricted. The voltage of 0V is applied to the assist gate on the left side of the assist gate AG1 to which the voltage of 5V is applied, so that the channel is cut off to stop the current flow.
The electrons from the source pass through the channel below the assist gate AG1, the floating gate FG of the cell, the assist gate AG2, the floating gate FG of the selected cell, and the assist gate AG3. Hot electrons are then injected into the floating gate of the selected cell, as the electric field on the boundary between the portion below the 1V-applied assist gate AG2 and the floating gate on the drain side.
During a reading operation, a voltage of 5V is applied to the assist gates AG on both sides of the subject floating gate, so that channels are formed thereunder, as shown in FIG. 2B. One of the channels is used as a source and the other one is used as a drain. In this manner, reading of the subject floating gate FG is performed.
Japanese Unexamined Patent Publication No. 2001-156275 discloses an AG-AND flash memory formed with SONOS-type memory cells. In this structure, two assist gates are provided between two diffusion regions that serve as a source and a drain, and SONOS-type memory cells are formed between the assist gates. The source and the drain are interchanged so as to trap electrons in the two nitride film regions of the memory cells in the vicinities of the assist gates. In this manner, two bits can be stored at once.
In the conventional AG-AND flash memory, however, sector transistors (ST Tr) connected to select gate lines are necessary to connect local bit lines to global bit lines DLm−3 through DLm+2. As a result, a larger circuit size is required. Also, with the technique disclosed by Y. Sasago, et al., there is a problem that the memory array area increases as the source and drain are formed without diffusion layers.